1. Field of the Invention
The present invention relates to a structure of a master-slice type semiconductor device, and more particularly relates to a structure of a cell array which is on a main surface thereof and formed into a shape of matrix by adjoining channel regions each other.
2. Related Background Art
Conventionally, in a case Of manufacturing a gate-array type semiconductor device and belongs to the field of the present invention, first a plurality of regions of a predetermined channel type is formed on a semiconductor wafer by doping a suitable impurity into the wafer. In the regions, there are a region (BC-P) in which a p-type active layer 30p is formed, and regions (BC-N1, BC-N2) in which an N-type active layer 30n is formed, and these regions are arrayed regularly to form a matrix shaped cell array. Continuously a gate electrode 40 is formed on the gate oxide in each active region. The semiconductor wafer at this stage is generally called master-slice (See FIG. 1).
Here, the general array of the P-type active layer and the N-type active layer (both constitute the cell array) for constituting the master-slice is shown in FIG. 2. In FIG. 2, regions indicated by a reference mark P and a reference mark N represent a P-channel region in which a P-channel transistor is formed and an N-channel region in which an N-channel transistor is formed, respectively. In this example, one P-channel region and a pair of a large and small N-channel regions form one basic cell.
It is noted that reference marks BC1 and BC2 represent a group of basic cells. Further, in FIG. 1 and FIG. 2, the P-channel region is indicated by BC-P, the N-channel region having a large area is indicated by BC-N1 (hereinafter called the first N-channel region), and the N-channel region having a small area is indicated by BC-N2 (hereinafter called the second N-channel region).
As shown in FIG. 1, for the ratio of area of each channel region constituting one basic cell, P-channel region (BC-P): the first N-channel region (BC-N1): the second N-channel region (BC-N2) is approximately 1:1:0.5.
Reasons for setting the area of each channel region constituting the basic cell to the above ratio are as follows.
In a case that a simple logical gate such as a NAND and a NOR, or a flip-flop is formed, usually a pair of one N-channel region and one P-channel region is utilized. In that case, for example, if an invertor is constituted in the aforesaid N-channel region, a gate width needs to be large, so that the N-channel region requires an area in which the gate width can be satisfactory wide taken (the first N-channel region BC-N1 is utilized).
On the other hand, in a case of forming a RAM, a transfer gate is further required. The transfer gate does not require a large driving capacity, so that the N-channel region which has a small area is utilized from the view point of an area efficiency (the second N-channel region BC-N2 is utilized).
Thus, conventionally one F-channel region (BC-P) and a pair of a large and small N-channel regions (BC-N1, BC-N2) constitute one basic cell. In the conventional master-slice, a combination of these three channel regions (a basic cell) is one constituent unit. In forming a circuit block by applying metal wiring, a simple logical gate can be wired on the basic cells which it was to be formed, but there needs a wiring region to wire between each logical gates. Accordingly, in a case of forming a wiring region shown as oblique lines in FIG. 2, a whole region in which one basic cell is to be formed is assigned for the wiring region, and the wiring region 20 has to be formed in an upper surface of the region. Usually, for the most cases, the wiring region 20 is formed on the both sides (equivalent to the upper and bottom side of FIG. 2) of each basic cell, therefore it is difficult to increase a use rate of gate to above 50%.